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Freescale Semiconductor /MK61F15WS /DDR /CR30

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Interpret as CR30

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)RSYNCRF 0RESERVED0INTSTAT0RESERVED0 (0)INTACK

RSYNCRF=0, INTACK=0

Description

DDR Control Register 30

Fields

RSYNCRF

Resynchroize after Refresh

0 (0): No effect

1 (1): Enable
RESERVED

Reserved
INTSTAT

Interrupt Status
RESERVED

Reserved
INTACK

Interupt Acknowlege

0 (0): No effect

1 (1): Clear the corresponding bit in INTSTATUS

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data